An Automatic Code Modification and Optimization System for High-Level Synthesis

Abstract

FPGA (Field Programmable Gate Array) has been used to recent studies and commercial products in high performance computation systems. Hardware Description Language(HDL) for FPGA is sometimes difficult for software engineers who do not have experience and knowledge of hardware design. Solving these issues, High-level Synthesis(HLS) Language, which generates HDL from C-based language automatically, has gathered attention recently. Most HLS provides compiler directives, a combination of sentences and numbers, to search better trade-off. By using this, trial-and-error process to achieve desire trade-off has became much earsier than HDL. Nevertheless to understand relationship between the directives and the final result, user are still required HLS depend experience. For this issue, we proposes an Automatic Code Modification for High-Level Synthesis (ACM-HLS), a tool for clarify the above mentioned relationship. In this paper, ACM-HLS focuses on loop optimization which has greate responsibility to speed-area tradeoff. For evaluations, we chose four applications, and achieves up to 66.0% speed up, and 52.3% speed up on average. Furthermore, our tool can also shows a tendency of optimization. Hence, users can chose the combination of directives even they do not have knowledge of experience.